In a computer system, for a given thread of computation, the next instruction to be executed after a conditional branch instruction in general depends upon the state of a condition. If the condition is of one state, the address of the next instruction to be executed may be simply the next sequential instruction address following the address of the conditional branch instruction, i.e., the fall-through address; whereas if the condition is of another state, the address of the next instruction to be executed will be the target address for the conditional branch instruction, which will usually be different from the next sequential address.
The evaluation of the condition associated with a conditional branch instruction may take several or more clock cycles, which may cause stalls among some pipelined processors. Furthermore, for an indirect conditional branch instruction (denoted as an "indirect branch instruction" for brevity), the target address is stored in a register. However, a pipelined processor may not read these registers until some number of pipe stages after instruction fetch, which may add to processor stalls.